The present invention relates to integrated circuits. More specifically, the present invention relates to a reduced-swing differential output buffer having an idle function.
High-speed data communication circuits frequently use differential output buffers for transmitting data over transmission media. In certain communication applications, there is a need to be able to reduce the differential output swing of the output buffer to zero while leaving the common-mode output level of the buffer unchanged.
One existing approach for reducing the differential output swing uses first and second differential output buffers, where the second differential output buffer drives the first differential output buffer. The differential output swing of the first differential buffer is reduced to zero by cutting the tail current supplied to the second differential buffer. This causes both outputs of the second differential buffer to go to a logic high voltage level. This approach is effective in reducing the differential output swing of the first differential buffer while leaving the common-mode level of the differential output buffer unchanged, but suffers from additional power consumption by the second differential buffer during normal operation.
A low-power differential output buffer is therefore desired which is capable of reducing the differential output swing of the buffer to zero while leaving the common-mode output level of the buffer unchanged.
One aspect of the present invention relates to a differential output buffer which includes first and second complementary data inputs, an idle input, and a differential output stage having first and second output stage control inputs and first and second differential data outputs. First and second push-pull circuits charge one of the first and second output stage control inputs toward a logic high voltage and discharge the other of the first and second output stage control inputs toward a logic low voltage based on relative logic states of the first and second data inputs. A logic low voltage supply generator is coupled to the idle input and the logic low voltage supply terminal for setting the logic low voltage as a function of the idle input.
Another aspect of the present invention relates to a differential output buffer which includes first and second complementary data inputs, an idle input, a current-mode differential output stage, first and second push-pull circuits and a voltage supply generator. The idle input has an active state and an inactive state. The differential output stage includes first and second differential data outputs and first and second output stage control inputs. The first push-pull circuit is biased in series between logic high and logic low voltage supply terminals and has first and second inputs coupled to the first and second data inputs, respectively, and an output coupled to the first output stage control input. The second push-pull circuit is biased in series between the logic high and logic low voltage supply terminals and has first and second inputs coupled to the second and first data inputs, respectively, and an output coupled to the second output stage control input. The voltage supply generator is coupled between the idle input and the logic low voltage supply terminal and generates a logic low voltage on the logic low voltage supply terminal when the idle input is in the inactive state and a logic high voltage on the logic low voltage supply terminal when the idle input is in the active state.
Another aspect of the present invention relates to a method of reducing a differential output swing of a differential output buffer. The method includes: providing a differential transistor pair between first and second differential data outputs and a tail current source, wherein the differential transistor pair comprises first and second output stage control inputs; receiving first and second complementary data inputs; receiving an idle input having an active state and an inactive state; driving the first and second output stage control inputs between a logic high voltage level and a logic low voltage level using P-channel type transistors, based on relative logic states of the first and second data inputs; and raising the logic low voltage level toward the logic high voltage level when the idle input is in the active state.